T&D-Bench

Página do Professor Sandro Neves Soares

T&D-Bench is a framework for design space exploration (DSE) of embedded processors, developed at UCS and at the UFRGS's Embedded Systems Lab. The framework aims at a fast design process, coupled to a great flexibility in modeling more complex or specific architectural mechanisms. For this purpose, the framework provides a specialized set of methods, tightly coupled to other modeling resources, to access and manipulate the processor model in addition to an easy-to-use description language. The T&D-Bench key features are:

the design methodology kernel is a component library where the description of processor datapath components is similar to VHDL behavioral descriptions of entities;
use of high-level modeling resources;
a reduced number of language elements (keywords, classes, and methods) that must be known by the designer to access these resources;
the availability of specific and orthogonal resources for the specification of the processor micro-architecture, instruction set, and timing;
it is an open-source and platform independent framework.

In this webpage, it can be found documentation describing the T&D-Bench design methodology, as well as there are some processor models that can be downloaded and employed for design space exploration or to teach Computer Architecture and Organization. Such models are simulated based on Assembly programs (which can be produced by the GNU gcc compiler) loaded by the user. The processor internal state is showed in a GUI during the program execution.

2010, July - Martin Hager, from HFU - Höhere Fachschule Uster, Switzerland, has been using the Neander and MIPS simulators with his students. He kindly sent us a Guide (in English) describing some aspects of these simulators - the guide is available at Tutorials.

2009, October, 12th -   an extension to a popular architectural feature, employed in the embedded processors market, were proposed and developed with T&D-Bench, in cooperation with researchers of the ACES group. This work will be presented at VLSI-SOC'2009

2008, October, 3rd   -   two papers based on T&D-Bench were selected for publication at WEAC'2008 and WPUC'2008

2008, June, 1st   -   a first version of the LC-3 simulator is available

2007, October, 24th   -   two papers based on T&D-Bench were presented at WEAC'2007 and WSCAD'2007, respectively (see more in section Papers)

2007, May, 15th   -   the framework for rISA experimentation (reduced bit-width Instruction Set Architecture) is now ready

2007, May, 11th   -   what we've done with T&D-Bench (its use in Education and also in research), in the last years, is described in the paper "From Classroom to Research: Providing Different Services for Computer Architecture Education", to be presented in the Workshop on Computer Architecture Education (WCAE'2007), in San Diego

2006, November, 1st   -   the version 1.0 of the MIPS simulators are available (monocycle, multicycle and pipelined versions). More information can be found in sections Software (how to download) and Models (how to execute)

2006, April, 29th   -   the paper "Design Space Exploration of Embedded Processors in Computer Architecture Education using T&D-Bench" will be presented at Frontiers in Education Conference